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Lattice Semiconductor
Functional Description
The Tx MAC reads data from the Tx Client FIFO when the client indicates a packet is available, and the Tx MAC is
in its appropriate state. The Tx MAC pre-fixes the Preamble and the Start-of-Frame Delimiter information to the
data and appends the Frame Check Sequence at the end of the data. In half-duplex operation, the Tx MAC stores
the first 64 bytes of data from the external FIFO in an internal buffer, to be used in re-transmitting data on collisions.
The SGMII Easy Connect configuration option adds pins and logic for seamless connection to the Lattice Gigabit
Ethernet PCS IP core.
Figure 2-3. Un-Tagged Ethernet Frame Format
PREAMBLE
SFD
DESTINATION
SOURCE
LENGTH/
DATA/PAD
FRAME CHECK
ADDRESS
ADDRESS
TYPE
SEQUENCE
7 bytes
1 byte
6 bytes
6 bytes
2 bytes
46-1500 bytes
4 bytes
Figure 2-4. VLAN-Tagged Ethernet Frame Format
PREAMBLE
SFD
DESTINATION
SOURCE
VLAN TAG
LENGTH/
DATA/PAD
FRAME CHECK
ADDRESS
ADDRESS
HEADER
TYPE
SEQUENCE
7 bytes
1 byte
6 bytes
6 bytes
4 bytes
2 bytes
46-1500 bytes
4 bytes
Figure 2-5. Ethernet Control Pause Frame Format
PREAMBLE
SFD
DESTINATION
ADDRESS
SOURCE
ADDRESS
LENGTH/TYPE
88-08
MAC CTL
OP_CODE
OP_CODE
PARAMS/RSV
FRAME CHECK
SEQUENCE
01-80-C2-00-00-01
00-01
7 bytes
1 byte
6 bytes
6 bytes
2 bytes
2 bytes
60 bytes
4 bytes
A Tagged frame includes a 4-byte VLAN Tag field, which is located between the Source Address field and the
Length/Type field. The VLAN Tag field includes the VLAN Identifier and other control information needed when
operating with Virtual Bridged LANs as described in IEEE P802.1Q.
IPUG51_03.0, December 2010
10
Tri-Speed Ethernet MAC User’s Guide
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